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IS42SM16200C is42rm16200c is42vm16200c 1 rev. a | mar. 2011 www.issi.com - dram@issi.com 1m x 16bits x 2banks low power synchronous dram description these is 42 sm/rm/vm 16200 c are low power 33, 554 , 432 bits cmos synchronous dram organized as 2 banks of 1 , 048 , 576 words x 16 bits . these products are offering fully synchronous operation and are referenced to a positive edge of the clock . all inputs and outputs are synchronized with the rising edge of the clock input . the data paths are internally pipelined to achieve high bandwidth . all input and output voltage levels are compatible with lvcmos . ? jedec standard 3.3v, 2.5v, 1.8v power supply. ? auto refresh and self refresh. ? all pins are compatible with lvcmos interface. ? 4k refresh cycle / 64ms. ? programmable burst length and burst type. - 1, 2, 4, 8 or full page for sequential burst. - 4 or 8 for interleave burst. ? programmable cas latency : 2,3 clocks. ? programmable driver strength control - full strength or 1/2, 1/4, 1/8 of full strength ? deep power down mode. ? all inputs and outputs referenced to the positive edge of the system clock. ? data mask function by dqm. ? internal dual banks operation. ? burst read single write operation. ? special function support. - pasr(partial array self refresh) - auto tcsr(temperature compensated self refresh) ? automatic precharge, includes concurrent auto precharge mode and controlled precharge. features copyright ? 2010 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this spe cif ication and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, pr odu cts or services described herein. customers are advised to obtain the latest version of this device specification before relying on any publi she d information and before placing orders for products. integrated silicon solution, inc. does not recommend the use of any of its products in life support applications where the fa ilu re or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. products are not authorized for use in such applications unless integrated silicon solution, inc. receives wri tte n assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of integrated silicon solution, inc is adequately protected under the circumstances
2 rev. a | mar. 2011 is42sm/rm/vm16200c www.issi.com - dram@issi.com figure1: 54ball fbga ball assignment [top view] a b c d e f g h j 1 2 3 4 5 6 7 8 9 vss dq15 vssq dq14 dq13 vddq dq12 dq11 vssq dq10 dq9 vddq udqm clk cke nc nc a9 a8 a7 a6 vss a5 a4 vddq dq0 vdd vssq dq2 dq1 vddq dq4 dq3 vssq dq6 dq5 /cas /ras /we ba nc /cs a0 a1 a10 a3 a2 vdd dq8 nc vss vdd ldqm dq7
3 rev. a | mar. 2011 is42sm/rm/vm16200c www.issi.com - dram@issi.com table2: pin descriptions pin pin name descriptions clk system clock the system clock input. all other inputs are registered to the sdram on the rising edge clk. cke clock enable controls internal clock signal and when deactivated, the sdram will be one of the states among power down, suspend or self refresh. /cs chip select enable or disable all inputs except clk, cke and dqm . ba bank address selects bank to be activated during ras activity. selects bank to be read/written during cas activity . a0~a10 address row address : ra0~ra10 column address : ca0~ca8 auto precharge : a10 /ras, /cas, /we row address strobe, column address strobe, write enable ras, cas and we define the operation . refer function truth table for details . ldqm,udqm data input/output mask controls output buffers in read mode and masks input data in write mode . dq0~dq15 data input/output data input/output pin . vdd/vss power supply/ground power supply for internal circuits and input buffers. vddq/vssq data output power/ground power supply for output buffers. nc no connection no connection.
4 rev. a | mar. 2011 is42sm/rm/vm16200c www.issi.com - dram@issi.com tcsr pasr figure2: functional block diagram control logic command decoder column address buffer & burst counter clock generator clk cke row address buffer & refresh counter /cs /ras /cas /we mode register bank b row decoder bank a row decoder sense amplifier column decoder & latch circuit dq dqm address data control circuit latch circuit input & output buffer extended mode register
5 rev. a | mar. 2011 is42sm/rm/vm16200c www.issi.com - dram@issi.com cke cke idle row active self refresh cbr refresh power down active power down read write read a write a pre - charge read suspend read a suspend write suspend write a suspend power on mode register set precharge cke cke cke cke cke cke read write cke cke read write pre act ref mrs automatic sequence manual input figure3: simplified state diagram extended mode register set deep power down
6 rev. a | mar. 2011 is42sm/rm/vm16200c www.issi.com - dram@issi.com wb burst type accesses within a given burst may be programmed to be either sequential or interleaved ; this is referred to as the burst type and is selected via bit m 3 . the ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in table 3 . table 3: burst definition m9 write burst mode 0 burst read and burst write 1 burst read and single write m3 burst type 0 sequential 1 interleave m6 m5 m4 cas latency 0 0 0 reserved 0 0 1 - 0 1 0 2 0 1 1 3 1 0 0 reserved 1 0 1 reserved 1 1 0 reserved 1 1 1 reserved m2 m1 m0 burst length m3 = 0 m3 = 1 0 0 0 1 1 0 0 1 2 2 0 1 0 4 4 0 1 1 8 8 1 0 0 reserved reserved 1 0 1 reserved reserved 1 1 0 reserved reserved 1 1 1 full page reserved burst length starting column address order of access within a burst sequential interleaved a2 a1 a0 2 0 0 - 1 0 - 1 1 1 - 0 1 - 0 4 0 0 0 - 1 - 2 - 3 0 - 1 - 2 - 3 0 1 1 - 2 - 3 - 0 1 - 0 - 3 - 2 1 0 2 - 3 - 0 - 1 2 - 3 - 0 - 1 1 1 3 - 0 - 1 - 2 3 - 2 - 1 - 0 8 0 0 0 0 - 1 - 2 - 3 - 4 - 5 - 6 - 7 0 - 1 - 2 - 3 - 4 - 5 - 6 - 7 0 0 1 1 - 2 - 3 - 4 - 5 - 6 - 7 - 0 1 - 0 - 3 - 2 - 5 - 4 - 7 - 6 0 1 0 2 - 3 - 4 - 5 - 6 - 7 - 0 - 1 2 - 3 - 0 - 1 - 6 - 7 - 4 - 5 0 1 1 3 - 4 - 5 - 6 - 7 - 0 - 1 - 2 3 - 2 - 1 - 0 - 7 - 6 - 5 - 4 1 0 0 4 - 5 - 6 - 7 - 0 - 1 - 2 - 3 4 - 5 - 6 - 7 - 0 - 1 - 2 - 3 1 0 1 5 - 6 - 7 - 0 - 1 - 2 - 3 - 4 5 - 4 - 7 - 6 - 1 - 0 - 3 - 2 1 1 0 6 - 7 - 0 - 1 - 2 - 3 - 4 - 5 6 - 7 - 4 - 5 - 2 - 3 - 0 - 1 1 1 1 7 - 0 - 1 - 2 - 3 - 4 - 5 - 6 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 full page n=a0 - 8 (location 0 - 511) c n , c n +1. c n +2, c n +3, c n +4? ?c n - 1, c n ... not supported note : 1 . for full - page accesses : y = 512 2 . for a burst length of two, a 1 - a 8 select the block - of - two burst ; a 0 selects the starting column within the block . 3 . for a burst length of four, a 2 - a 8 select the block - of - four burst ; a 0 - a 1 select the starting column within the block . 4 . for a burst length of eight, a 3 - a 8 select the block - of - eight burst ; a 0 - a 2 select the starting column within the block . 5 . for a full - page burst, the full row is selected and a 0 - a 8 select the starting column . 6 . whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block . 7 . for a burst length of one, a 0 - a 8 select the unique column to be accessed, and mode register bit m 3 is ignored . 0 cas latency bt burst length address bus 0 1 2 3 4 5 6 10 9 8 7 11 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 ba mode register (mx) 0 0 0 figure4: mode register definition note: m11(ba) must be set to ?0? to select mode register (vs. the extended mode register)
7 rev. a | mar. 2011 is42sm/rm/vm16200c www.issi.com - dram@issi.com 1 pasr figure5: extended mode register address bus extended mode register (ex) 0 1 2 3 4 5 6 10 9 8 7 11 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 ba e2 e1 e0 self refresh coverage 0 0 0 all banks 0 0 1 one bank (ba=0) 0 1 0 reserved 0 1 1 reserved 1 0 0 reserved 1 0 1 half of one bank (ba=0, row address msb=0) 1 1 0 quarter of one bank (ba=0, row address 2 msb=0) 1 1 1 reserved note: e11(ba) must be set to ?1? to select extend mode register (vs. the base mode register) e6 e5 driver strength 0 0 full strength 0 1 1/2 strength 1 0 1/4 strength 1 1 1/8 strength 0 0 0 0 ds tcsr e4 e3 maximum case temp. 0 0 85 0 1 70 1 0 45 1 1 auto
8 rev. a | mar. 2011 is42sm/rm/vm16200c www.issi.com - dram@issi.com in general, this 32 mb sdram ( 1 m x 16 bits x 2 banks) is a dual - bank dram that operates at 3 . 0 v/ 3 . 3 v and includes a synchronous interface (all signals are registered on the positive edge of the clock signal, clk) . each of the 16, 777 , 216 - bit banks is organized as 2 , 048 rows by 512 columns by 16- bits read and write accesses to the sdram are burst oriented ; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence . accesses begin with the registration of an active command, which is then followed by a read or write command . the address bits registered coincident with the active command are used to select the bank and row to be accessed (ba select the bank, a 0 - a 10 select the row) . the address bits (ba select the bank, a 0 - a 8 select the column) registered coincident with the read or write command are used to select the starting column location for the burst access . prior to normal operation, the sdram must be initialized . the following sections provide detailed information covering device initialization, register definition, command descriptions and device operation . power up and initialization sdrams must be powered up and initialized in a predefined manner . operational procedures other than those specified may result in undefined operation . once power is applied to vdd and vddq(simultaneously) and the clock is stable(stable clock is defined as a signal cycling within timing constraints specified for the clock pin), the sdram requires a 100s delay prior to issuing any command other than a command inhibit or nop . cke must be held high during the entire initialization period until the precharge command has been issued . starting at some point during this 100s period and continuing at least through the end of this period, command inhibit or nop commands should be applied . once the 100s delay has been satisfied with at least one command inhibit or nop command having been applied, a precharge command should be applied . all banks must then be precharged, thereby placing the device in the all banks idle state . once in the idle state, two auto refresh cycles must be performed . after the auto refresh cycles are complete, the sdram is ready for mode register programming . because the mode register will power up in an unknown state, it should be loaded prior to applying any operational command . and a extended mode register set command will be issued to program specific mode of self refresh operation(pasr) . the following these cycles, the low power sdram is ready for normal operation . register definition mode register the mode register is used to define the specific mode of operation of the sdram . this definition includes the selection of a burst length, a burst type, a cas latency, an operating mode and a write burst mode . the mode register is programmed via the load mode register command and will retain the stored information until it is programmed again or the device loses power . mode register bits m 0 - m 2 specify the burst length, m 3 specifies the type of burst (sequential or interleaved), m 4 - m 6 specify the cas latency, m 7 and m 8 specify the operating mode, m 9 specifies the write burst mode, and m 10 should be set to zero . m 11 should be set to zero to prevent extended mode register . the mode register must be loaded when all banks are idle, and the controller must wait the specified time before initiating the subsequent operation . violating either of these requirements will result in unspecified operation . functional description extended mode register the extended mode register controls the functions beyond those controlled by the mode register . these additional functions are special features of the batram device . they include temperature compensated self refresh (tcsr) control, and partial array self refresh (pasr) and driver strength (ds) . the extended mode register is programmed via the mode register set command (ba= 1 ) and retains the stored information until it is programmed again or the device loses power . the extended mode register must be programmed with m 7 through m 10 set to ? 0 ? . the extended mode register must be loaded when all banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating any subsequent operation . violating either of these requirements results in unspecified operation .
9 rev. a | mar. 2011 is42sm/rm/vm16200c www.issi.com - dram@issi.com burst length read and write accesses to the sdram are burst oriented, with the burst length being programmable, as shown in figure 4 . the burst length determines the maximum number of column locations that can be accessed for a given read or write command . burst lengths of 1 , 2 , 4 or 8 locations are available for both the sequential and the interleaved burst types, and a full - page burst is available for the sequential type . the full - page burst is used in conjunction with the burst terminate command to generate arbitrary burst lengths . reserved states should not be used, as unknown operation or incompatibility with future versions may result . when a read or write command is issued, a block of columns equal to the burst length is effectively selected . all accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached . the block is uniquely selected by a 1 - a 8 when the burst length is set to two ; by a 2 - a 8 when the burst length is set to four ; and by a 3 - a 8 when the burst length is set to eight . the remaining (least significant) address bit(s) is (are) used to select the starting location within the block . full - page bursts wrap within the page if the boundary is reached . bank(row) active the bank active command is used to activate a row in a specified bank of the device. this command is initiated by activating cs, ras and deasserting cas, we at the positive edge of the clock. the value on the ba selects the bank, and the value on the a0 - a10 select s the row. this row remains active for column access until a precharge command is issued to that bank. read and write operations can onl y be initiated on this activated bank after the minimum trcd time is passed from the activate command. read the read command is used to initiate the burst read of data. this command is initiated by activating cs, cas, and deasserting we , ras at the positive edge of the clock. ba input select the bank, a0 - a8 address inputs select the starting column location. the value o n input a10 determines whether or not auto precharge is used. if auto precharge is selected the row being accessed will be precharged at th e end of the read burst; if auto precharge is not selected, the row will remain active for subsequent accesses. the length of burst an d the cas latency will be determined by the values programmed during the mrs command. write the write command is used to initiate the burst write of data. this command is initiated by activating cs, cas, we and deasse rti ng ras at the positive edge of the clock. ba input select the bank, a0 - a8 address inputs select the starting column location. the valu e on input a10 determines whether or not auto precharge is used. if auto precharge is selected the row being accessed will be precharged a t the end of the write burst; if auto precharge is not selected, the row will remain active for subsequent accesses.
10 rev. a | mar. 2011 is42sm/rm/vm16200c www.issi.com - dram@issi.com cas latency the cas latency is the delay, in clock cycles, between the registration of a read command and the availability of the first piece of output data . the latency can be set to two or three clocks . if a read command is registered at clock edge n, and the latency is m clocks, the data will be available by clock edge n + m . the dqs will start driving as a result of the clock edge one cycle earlier (n + m - 1 ), and provided that the relevant access times are met, the data will be valid by clock edge n + m . for example, assuming that the clock cycle time is such that all relevant access times are met, if a read command is registered at t 0 and the latency is programmed to two clocks, the dqs will start driving after t 1 and the data will be valid by t 2 , as shown in figure 6 . reserved states should not be used as unknown operation or incompatibility with future versions may result . operating mode the normal operating mode is selected by setting m 7 and m 8 to zero ; the other combinations of values for m 7 and m 8 are reserved for future use and/or test modes . the programmed burst length applies to both read and write bursts . test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result . write burst mode when m 9 = 0 , the burst length programmed via m 0 - m 2 applies to both read and write bursts ; when m 9 = 1 , the programmed burst length applies to read bursts, but write accesses are single - location (nonburst) accesses . clk command dq nop nop dout t0 t1 t2 tlz toh tac cas latency=2 t3 read clk command dq nop nop dout t0 t1 t2 tlz toh tac cas latency=3 t3 nop t4 read don?t care undefined figure6: cas latency
11 rev. a | mar. 2011 is42sm/rm/vm16200c www.issi.com - dram@issi.com table4: command truth table function cken - 1 cken /cs /ras /cas /we dqm addr a10 note command inhinit (nop) h x h x x x x x no operation (nop) h x l h h h x x mode register set h x l l l l x op code 4 extended mode register set h x l l l l x op code 4 active (select bank and activate row) h x l l h h x bank/row read h x l h l h l/h bank/col l 5 read with autoprecharge h x l h l h l/h bank/col h 5 write h x l h l l l/h bank/col l 5 write with autoprecharge h x l h l l l/h bank/col h 5 precharge all banks h x l l h l x x h precharge selected bank h x l l h l x bank l burst stop h h l h h l x x auto refresh h h l l l h x x 3 self refresh entry h l l l l h x x 3 self refresh exit l h h x x x x x 2 l h h h precharge power down entry h l h x x x x x l h h h precharge down exit l h h x x x x x l h h h clock suspend entry h l h x x x x x l v v v clock suspend exit l h x x x deep power down entry h l l h h l x x 6 deep power down exit l h x x x note : 1. cken is the logic state of cke at clock edge n; cken - 1 was the state of cke at the previous clock edge. h: high level, l: low level, x: don't care, v: valid 2. exiting self refresh occurs by asynchronously bringing cke from low to high and will put the device in the all banks idle sta te once txsr is met. command inhibit or nop commands should be issued on any clock edges occuring during the txsr period. a minimum of two nop commands must be provided during txsr period. 3. during refresh operation, internal refresh counter controls row addressing; all inputs and i/os are ?don?t care? except fo r c ke. 4. a0 - a10 define op code written to the mode register, and ba must be issued 0 in the mode register set, and 1 in the extended mode register set. 5. dqm ?l? means the data write/ouput enable and ?h? means the write inhibit/output high - z. write dqm latency is 0 clk and read dqm latency is 2 clk. 6. standard sdram parts assign this command sequence as burst terminate. for bat ram parts, the burst terminate command is assigned to the deep power down function.
12 rev. a | mar. 2011 is42sm/rm/vm16200c www.issi.com - dram@issi.com table5: function truth table current state command action note /cs /ras /cas /we ba a0 - a10 description idle l l l l op code mode register set set the mode register 14 l l l h x x auto or self refresh start auto or self refresh 5 l l h l ba x precharge no operation l l h h ba row add. bank activate activate the specified bank and row l h l l ba col add./ a10 write/writeap illegal 4 l h l h ba col add./ a10 read/readap illegal 4 l h h h x x no operation no operation 3 h x x x x x device deselect no operation or power down 3 row active l l l l op code mode register set illegal 13,14 l l l h x x auto or self refresh illegal 13 l l h l ba x precharge precharge 7 l l h h ba row add. bank activate illegal 4 l h l l ba col add./a10 write/write ap start write : optional ap(a10=h) 6 l h l h ba col add./a10 read/read ap start read : optional ap(a10=h) 6 l h h h x x no operation no operation h x x x x x device deselect no operation read l l l l op code mode register set illegal 13,14 l l l h x x auto or self refresh illegal 13 l l h l ba x precharge termination burst : start the precharge l l h h ba row add. bank activate illegal 4 l h l l ba col add./a10 write/writeap termination burst : start write(ap) 8,9 l h l h ba col add./a10 read/read ap terimination burst : start read(ap) 8 l h h h x x no operation continue the burst h x x x x x device deselect continue the burst
13 rev. a | mar. 2011 is42sm/rm/vm16200c www.issi.com - dram@issi.com table5: function truth table current state command action note /cs /ras /cas /we ba a0 - a10 description write l l l l op code mode register set illegal 13,14 l l l h x x auto or self refresh illegal 13 l l h l ba x precharge termination burst : start the precharge 10 l l h h ba row add. bank activate illegal 4 l h l l ba col add./a10 write/writeap termination burst : start write(ap) 8 l h l h ba col add./a10 read/readap terimination burst : start read(ap) 8,9 l h h h x x no operation continue the burst h x x x x x device deselect continue the burst read with auto precharge l l l l op code mode register set illegal 13,14 l l l h x x auto or self refresh illegal 13 l l h l ba x precharge illegal 4,12 l l h h ba row add. bank activate illegal 4,12 l h l l ba col add./a10 write/writeap illegal 12 l h l h ba col add./a10 read/readap illegal 12 l h h h x x no operation continue the burst h x x x x x device deselect continue the burst write with auto precharge l l l l op code mode register set illegal 13,14 l l l h x x auto or self refresh illegal 13 l l h l ba x precharge illegal 4,12 l l h h ba row add. bank activate illegal 4,12 l h l l ba col add./a10 write/writeap illegal 12 l h l h ba col add./a10 read/readap illegal 12 l h h h x x no operation continue the burst h x x x x x device deselect continue the burst
14 rev. a | mar. 2011 is42sm/rm/vm16200c www.issi.com - dram@issi.com table5: function truth table current state command action note /cs /ras /cas /we ba a0 - a10 description precharging l l l l op code mode register set illegal 13,14 l l l h x x auto or self refresh illegal 13 l l h l ba x precharge no operation : bank(s) idle after trp l l h h ba row add. bank activate illegal 4,12 l h l l ba col add./ a10 write/writeap illegal 4,12 l h l h ba col add./ a10 read/readap illegal 4,12 l h h h x x no operation no operation : bank(s) idle after trp h x x x x x device deselect no operation : bank(s) idle after trp row activating l l l l op code mode register set illegal 13,14 l l l h x x auto or self refresh illegal 13 l l h l ba x precharge illegal 4,12 l l h h ba row add. bank activate illegal 4,11,12 l h l l ba col add./a10 write/write ap illegal 4,12 l h l h ba col add./a10 read/read ap illegal 4,12 l h h h x x no operation no operation : row active after trcd h x x x x x device deselect no operation : row active after trcd write recovering l l l l op code mode register set illegal 13,14 l l l h x x auto or self refresh illegal 13 l l h l ba x precharge illegal 4,13 l l h h ba row add. bank activate illegal 4,12 l h l l ba col add./a10 write/writeap start write : optional ap(a10=h) l h l h ba col add./a10 read/read ap start write : optional ap(a10=h) 9 l h h h x x no operation no operation : row active after tdpl h x x x x x device deselect no operation : row active after tdpl
15 rev. a | mar. 2011 is42sm/rm/vm16200c www.issi.com - dram@issi.com table5: function truth table current state command action note /cs /ras /cas /we ba a0 - a10 description write recovering with auto precharge l l l l op code mode register set illegal 13,14 l l l h x x auto or self refresh illegal 13 l l h l ba x precharge illegal 4,13 l l h h ba row add. bank activate illegal 4,12 l h l l ba col add./ a10 write/writeap illegal 4,12 l h l h ba col add./ a10 read/readap illegal 4,9,12 l h h h x x no operation no operation : precharge after tdpl h x x x x x device deselect no operation : precharge after tdpl refreshing l l l l op code mode register set illegal 13,14 l l l h x x auto or self refresh illegal 13 l l h l ba x precharge illegal 13 l l h h ba row add. bank activate illegal 13 l h l l ba col add./a10 write/write ap illegal 13 l h l h ba col add./a10 read/read ap illegal 13 l h h h x x no operation no operation : idle after trc h x x x x x device deselect no operation : idle after trc mode register accessing l l l l op code mode register set illegal 13,14 l l l h x x auto or self refresh illegal 13 l l h l ba x precharge illegal 13 l l h h ba row add. bank activate illegal 13 l h l l ba col add./a10 write/writeap illegal 13 l h l h ba col add./a10 read/read ap illegal 13 l h h h x x no operation no operation : idle after 2 clock cycle h x x x x x device deselect no operation : idle after 2 clock cycle
16 rev. a | mar. 2011 is42sm/rm/vm16200c www.issi.com - dram@issi.com note : 1. h: logic high, l: logic low, x: don't care, ba: bank address, ap: auto precharge. 2. all entries assume that cke was active during the preceding clock cycle. 3. if both banks are idle and cke is inactive, then in power down cycle 4. illegal to bank in specified states. function may be legal in the bank indicated by bank address, depending on the state of that bank. 5. if both banks are idle and cke is inactive, then self refresh mode. 6. illegal if trcd is not satisfied. 7. illegal if tras is not satisfied. 8. must satisfy burst interrupt condition. 9. must satisfy bus contention, bus turn around, and/or write recovery requirements. 10. must mask preceding data which don't satisfy tdpl. 11. illegal if trrd is not satisfied 12. illegal for single bank, but legal for other banks in multi - bank devices. 13. illegal for all banks. 14. mode register set and extended mode register set is same command truth table except ba.
17 rev. a | mar. 2011 is42sm/rm/vm16200c www.issi.com - dram@issi.com table6: cke truth table current state cke command action note prev cycle current cycle /cs /ras /cas /we ba a0 - a10 self refresh h x x x x x x x invalid 2 l h h x x x x x exit self refresh with device deselect 3 l h l h h h x x exit self refresh with no operation 3 l h l h h l x x illegal 3 l h l h l x x x illegal 3 l h l l x x x x illegal 3 l l x x x x x x maintain self refresh power down h x x x x x x x invalid 2 l h h x x x x x power down mode exit, all banks idle 3 l h h h x x l h l l x x x x illegal 3 x l x x x x x l x x l l x x x x x x maintain power down mode deep power down h x x x x x x x invalid 2 l h x x x x x x deep power down mode exit 6 l l x x x x x x maintain deep power down mode all banks idle h h h x x x refer to the idle state section of the current state truth table 4 h h l h x x 4 h h l l h x 4 h h l l l h x x auto refresh h h l l l l op code mode register set 5 h l h x x x refer to the idle state section of the current state truth table 4 h l l h x x 4 h l l l h x 4 h l l l l h x x entry self refresh 5 h l l l l l op code mode register set l x x x x x x x power down 5 any state other than listed above h h x x x x x x refer to operations of the current state truth table h l x x x x x x begin clock suspend next cycle l h x x x x x x exit clock suspend next cycle l l x x x x x x maintain clock suspend
18 rev. a | mar. 2011 is42sm/rm/vm16200c www.issi.com - dram@issi.com note : 1. h: logic high, l: logic low, x: don't care 2. for the given current state cke must be low in the previous cycle. 3. when cke has a low to high transition, the clock and other inputs are re - enabled asynchronously. when exiting power down mode , a nop (or device deselect) command is required on the first positive edge of clock after cke goes high. 4. the address inputs depend on the command that is issued. 5. the precharge power down mode, the self refresh mode, and the mode register set can only be entered from the all banks idl e s tate. 6. when cke has a low to high transition, the clock and other inputs are re - enabled asynchronously. when exiting deep power down mode, a nop (or device deselect) command is required on the first positive edge of clock after cke goes high and is maintained for a minimum 100usec.
19 rev. a | mar. 2011 is42sm/rm/vm16200c www.issi.com - dram@issi.com table7a: 3.3v absolute maximum rating parameter symbol rating unit ambient temperature (industrial) t a - 40 ~ 85 c ambient temperature (commercial) 0 ~ 70 storage temperature t stg - 55 ~ 150 c voltage on any pin relative to vss v in , v out - 1.0 ~ 4.6 v voltage on vdd relative to vss vdd, vddq - 1.0 ~ 4.6 v short circuit output current i os 50 ma power dissipation p d 1 w note : stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device . this is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied . exposure to absolute maximum rating conditions for extended periods may affect reliability . table8a: 3.3v capacitance (t a =25 c, f=1mhz, vdd=3.3v) parameter pin symbol min max unit input capacitance clk c i1 2 4 pf a0~a10, ba, cke, /cs, /ras, /cas, /we, l(u)dqm c i2 2 4 pf data input/output capacitance dq0~dq15 c io 3 5 pf table9a: 3.3v dc operating condition (voltage referenced to vss=0v, t a = - 40 ~ 85 c) parameter symbol min typ max unit note power supply voltage vdd 2.7 3.3 3.6 v vddq 2.7 3.3 3.6 v 1 input high voltage v ih 2.2 - vddq+0.3 v 2 input low voltage v il - 0.3 0 0.5 v 3 output high voltage v oh 2.4 - - v i oh = - 0.1ma output low voltage v ol - - 0.4 v i ol = + 0.1 ma input leakage current i li - 1 - 1 ua 4 output leakage current i lo - 1.5 1.5 ua 5 note : 1. vddq must not exceed the level of vdd 2. vih(max) = 5.3v ac. the overshoot voltage duration is 3ns. 3. vil(min) = - 2.0v ac. the overshoot voltage duration is 3ns. 4. any input 0v vin vddq. input leakage currents include hi - z output leakage for all bi - directional buffers with tri - state outputs. 5. dout is disabled, 0v vout vddq.
20 rev. a | mar. 2011 is42sm/rm/vm16200c www.issi.com - dram@issi.com table10a: 3.3v ac operating condition (t a = - 40 ~ 85 c, vdd = 2.7v - 3.6v , vss=0v ) parameter symbol value unit ac input high/low level voltage v ih / v il 2.4 / 0. 4 v input timing measurement reference level voltage v trip 0.5 x vddq v input rise / fall time t r / t f 1 / 1 ns output timing measurement reference level voltage v outref 0.5 x vddq v output load capacitance for access time measurement c l 30 pf output 870? 1200? vddq 30pf output 30pf 50? vtt=0.5 x vddq z0=50 ? dc output load circuit ac output load circuit
21 rev. a | mar. 2011 is42sm/rm/vm16200c www.issi.com - dram@issi.com table7b: 2.5v absolute maximum rating parameter symbol rating unit ambient temperature (industrial) t a - 40 ~ 85 c ambient temperature (commercial) 0 ~ 70 storage temperature t stg - 55 ~ 150 c voltage on any pin relative to vss v in , v out - 1.0 ~ 3.6 v voltage on vdd relative to vss vdd, vddq - 1.0 ~ 3.6 v short circuit output current i os 50 ma power dissipation p d 1 w note : stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device . this is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied . exposure to absolute maximum rating conditions for extended periods may affect reliability . table8b: 2.5v capacitance (t a =25 c, f=1mhz, vdd=2.5v) parameter pin symbol min max unit input capacitance clk c i1 2 4 pf a0~a10, ba, cke, /cs, /ras, /cas, /we, l(u)dqm c i2 2 4 pf data input/output capacitance dq0~dq15 c io 3 5 pf table9b: 2.5v dc operating condition (voltage referenced to vss=0v, t a = - 40 ~ 85 c) parameter symbol min typ max unit note power supply voltage vdd 2.3 2.5 3.0 v vddq 2.3 2.5 3.0 v 1 input high voltage v ih 0.8 x vddq - vddq+0.3 v 2 input low voltage v il - 0.3 0 0. 3 v 3 output high voltage v oh 0.9 x vddq - - v i oh = - 0.1ma output low voltage v ol - - 0. 2 v i ol = + 0.1 ma input leakage current i li - 1 - 1 ua 4 output leakage current i lo - 1.5 1.5 ua 5 note : 1. vddq must not exceed the level of vdd 2. vih(max) = vddq+1.5 v ac. the overshoot voltage duration is 3ns. 3. vil(min) = - 1 .0v ac. the overshoot voltage duration is 3ns. 4. any input 0v vin vddq. input leakage currents include hi - z output leakage for all bi - directional buffers with tri - state outputs. 5. dout is disabled, 0v vout vddq.
22 rev. a | mar. 2011 is42sm/rm/vm16200c www.issi.com - dram@issi.com table10b: 2.5v ac operating condition (t a = - 40 ~ 85 c, vdd = 2.3v - 3.0v , vss=0v ) parameter symbol value unit ac input high/low level voltage v ih / v il 0.9 x vddq / 0.2 v input timing measurement reference level voltage v trip 0.5 x vddq v input rise / fall time t r / t f 1 / 1 ns output timing measurement reference level voltage v outref 0.5 x vddq v output load capacitance for access time measurement c l 30 pf output 500? 500? vddq 30pf output 30pf 50? vtt=0.5 x vddq z0=50 ? dc output load circuit ac output load circuit
23 rev. a | mar. 2011 is42sm/rm/vm16200c www.issi.com - dram@issi.com table7c: 1.8v absolute maximum rating parameter symbol rating unit ambient temperature (industrial) t a - 40 ~ 85 c ambient temperature (commercial) 0 ~ 70 storage temperature t stg - 55 ~ 150 c voltage on any pin relative to vss v in , v out - 1.0 ~ 2.6 v voltage on vdd relative to vss vdd, vddq - 1.0 ~ 2.6 v short circuit output current i os 50 ma power dissipation p d 1 w note : stresses greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device . this is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied . exposure to absolute maximum rating conditions for extended periods may affect reliability . table8c: 1.8v capacitance (t a =25 c, f=1mhz, vdd= 1.8 v) parameter pin symbol min max unit input capacitance clk c i1 2 4 pf a0~a10, ba, cke, /cs, /ras, /cas, /we, l(u)dqm c i2 2 4 pf data input/output capacitance dq0~dq15 c io 3 5 pf table9c: 1.8v dc operating condition (voltage referenced to vss=0v, t a = - 40 ~ 85 c) parameter symbol min typ max unit note power supply voltage vdd 1.7 1.8 1.95 v vddq 1.7 1.8 1.95 v 1 input high voltage v ih 0.8 x vddq - vddq+0.3 v 2 input low voltage v il - 0.3 0 0. 3 v 3 output high voltage v oh 0.9 x vddq - - v i oh = - 0.1ma output low voltage v ol - - 0. 2 v i ol = + 0.1 ma input leakage current i li - 1 - 1 ua 4 output leakage current i lo - 1.5 1.5 ua 5 note : 1. vddq must not exceed the level of vdd 2. vih(max) = vddq+1.5 v ac. the overshoot voltage duration is 3ns. 3. vil(min) = - 1 .0v ac. the overshoot voltage duration is 3ns. 4. any input 0v vin vddq. input leakage currents include hi - z output leakage for all bi - directional buffers with tri - state outputs. 5. dout is disabled, 0v vout vddq.
24 rev. a | mar. 2011 is42sm/rm/vm16200c www.issi.com - dram@issi.com table10c: 1.8v ac operating condition (t a = - 40 ~ 85 c, vdd = 1.7v - 1.95v, vss=0v ) parameter symbol value unit ac input high/low level voltage v ih / v il 0.9 x vddq / 0.2 v input timing measurement reference level voltage v trip 0.5 x vddq v input rise / fall time t r / t f 1 / 1 ns output timing measurement reference level voltage v outref 0.5 x vddq v output load capacitance for access time measurement c l 30 pf output 500? 500? vddq 30pf output 30pf 50? vtt=0.5 x vddq z0=50 ? dc output load circuit ac output load circuit
25 rev. a | mar. 2011 is42sm/rm/vm16200c www.issi.com - dram@issi.com table11a: 3.3v dc characteristic (dc operating conditions unless otherwise noted) parameter sym test condition speed unit note - 60 - 75 operating current icc1 burst length=1, one bank active, trc trc(min) iol = 0 ma 50 ma 1 precharge standby current in power down mode icc2p cke vil(max), tck = 10ns 80 ua icc2ps cke & clk vil(max), tck = 80 precharge standby current in non power down mode icc2n cke vih(min), /cs vih(min), tck = 10ns input signals are changed one time during 2 clks. 9 ma icc2ns cke vih(min), clk vil(max), tck = input signals are stable. 5 active standby current in power down mode icc3p cke vil(max), tck = 10ns 1.0 ma icc3ps cke & clk vil(max), tck = 0.5 active standby current in non power down mode icc3n cke vih(min), /cs vih(min), tck = 10ns input signals are changed one time during 2 clks. 18 ma icc3ns cke vih(min), clk vil(max), tck = input signals are stable. 10 burst mode operating current icc4 tck>tck(min), iol = 0 ma, page burst all banks activated, tccd = 1 clk 60 55 ma 1 auto refresh current (4k cycle) icc5 trc trfc(min), all banks active 40 ma 2 self refresh current pasr tcsr icc6 cke 0.2v ua 2 banks 45~85 c 200 - 25~45 c 170 1 bank 45~85 c 180 - 25~45 c 150 deep power down mode current icc7 10 ua note : 1. measured with outputs open. 2. refresh period is 64ms.
26 rev. a | mar. 2011 is42sm/rm/vm16200c www.issi.com - dram@issi.com table11b: 2.5v dc characteristic (dc operating conditions unless otherwise noted) parameter sym test condition speed unit note - 60 - 75 operating current icc1 burst length=1, one bank active, trc trc(min) iol = 0 ma 50 ma 1 precharge standby current in power down mode icc2p cke vil(max), tck = 10ns 80 ua icc2ps cke & clk vil(max), tck = 80 precharge standby current in non power down mode icc2n cke vih(min), /cs vih(min), tck = 10ns input signals are changed one time during 2 clks. 9 ma icc2ns cke vih(min), clk vil(max), tck = input signals are stable. 5 active standby current in power down mode icc3p cke vil(max), tck = 10ns 1.0 ma icc3ps cke & clk vil(max), tck = 0.5 active standby current in non power down mode icc3n cke vih(min), /cs vih(min), tck = 10ns input signals are changed one time during 2 clks. 18 ma icc3ns cke vih(min), clk vil(max), tck = input signals are stable. 10 burst mode operating current icc4 tck>tck(min), iol = 0 ma, page burst all banks activated, tccd = 1 clk 60 55 ma 1 auto refresh current (4k cycle) icc5 trc trfc(min), all banks active 40 ma 2 self refresh current pasr tcsr icc6 cke 0.2v ua 2 banks 45~85 c 200 - 25~45 c 170 1 bank 45~85 c 180 - 25~45 c 150 deep power down mode current icc7 10 ua note : 1. measured with outputs open. 2. refresh period is 64ms.
27 rev. a | mar. 2011 is42sm/rm/vm16200c www.issi.com - dram@issi.com table11c: 1.8v dc characteristic (dc operating conditions unless otherwise noted) parameter sym test condition speed unit note - 60 - 75 operating current icc1 burst length=1, one bank active, trc trc(min) iol = 0 ma 50 ma 1 precharge standby current in power down mode icc2p cke vil(max), tck = 10ns 80 ua icc2ps cke & clk vil(max), tck = 80 precharge standby current in non power down mode icc2n cke vih(min), /cs vih(min), tck = 10ns input signals are changed one time during 2 clks. 9 ma icc2ns cke vih(min), clk vil(max), tck = input signals are stable. 5 active standby current in power down mode icc3p cke vil(max), tck = 10ns 1.0 ma icc3ps cke & clk vil(max), tck = 0.5 active standby current in non power down mode icc3n cke vih(min), /cs vih(min), tck = 10ns input signals are changed one time during 2 clks. 18 ma icc3ns cke vih(min), clk vil(max), tck = input signals are stable. 10 burst mode operating current icc4 tck>tck(min), iol = 0 ma, page burst all banks activated, tccd = 1 clk 60 55 ma 1 auto refresh current (4k cycle) icc5 trc trfc(min), all banks active 40 ma 2 self refresh current pasr tcsr icc6 cke 0.2v ua 2 banks 45~85 c 200 - 25~45 c 170 1 bank 45~85 c 180 - 25~45 c 150 deep power down mode current icc7 10 ua note : 1. measured with outputs open. 2. refresh period is 64ms.
28 rev. a | mar. 2011 is42sm/rm/vm16200c www.issi.com - dram@issi.com table12: ac characteristic (ac operation conditions unless otherwise noted) parameter sym - 60 - 75 unit note min max min max clk cycle time cl = 3 tck3 6.0 1000 7.5 1000 ns 1 cl = 2 tck2 10 10 access time from clk (pos. edge) cl = 3 tac3 5.5 6 2 cl = 2 tac2 8 8 clk high - level width tch 2.5 2.5 3 clk low - level width tcl 2.5 2.5 3 cke setup time tcks 1.5 2.0 cke hold time tckh 1.0 1.0 /cs, /ras, /cas, /we, dqm setup time tcms 1.5 2.0 /cs, /ras, /cas, /we, dqm hold time tcmh 1.0 1.0 address setup time tas 1.5 2.0 address hold time tah 1.0 1.0 data - in setup time tds 1.5 2.0 data - in hold time tdh 1.0 1.0 data - out high - impedance time from clk (pos.edge) cl = 3 thz3 5.5 6 4 cl = 2 thz2 8 8 data - out low - impedance time tlz 1.0 1.0 data - out hold time (load) toh 2.5 2.5 data - out hold time (no load) tohn 1.8 1.8 active to precharge command tras 42 100k 45 100k precharge command period trp 18 22.5 active bank a to active bank a command trc 60 67.5 5 active bank a to active bank b command trrd 12 15 active to read or write delay trcd 18 22.5 read/write command to read/write command tccd 1 1 clk 6 write command to input data delay tdwd 0 0 6 data - in to precharge command tdpl 12 15 ns 7 data - in to active command tdal 30 37.5 7 dqm to data high - impedance during reads tdqz 2 2 clk 6 dqm to data mask during writes tdqm 0 0 6 load mode register command to active or refresh command tmrd 2 2 8 data - out to high - impedance from precharge command cl = 3 troh3 3 3 6 cl = 2 troh2 2 2 last data - in to burst stop command tbdl 1 1 6 last data - in to new read/write command tcdl 1 1 6 cke to clock disable or power - down entry mode tcked 1 1 clk 9 cke to clock enable or power - down exit setup mode tped 1 1 9 refresh period (4,096 refresh cycles) tref 64 64 ms auto refresh period trfc 80 80 ns 5 exit self refresh to active command txsr 80 80 5 transition time tt 0.5 1.2 0.5 1.2
29 rev. a | mar. 2011 is42sm/rm/vm16200c www.issi.com - dram@issi.com note : 1 . the clock frequency must remain constant (stable clock is defined as a signal cycling within timing constraints specified for the clock pin) during access or precharge states (read, write, including tdpl, and precharge commands) . cke may be used to reduce the data rate . 2 . tac at cl = 3 with no load is 5 . 5 ns and is guaranteed by design . access time to be measured with input signals of 1 v/ns edge rate, from 0 . 8 v to 0 . 2 v. if tr > 1 ns, then (tr/ 2 - 0 . 5 )ns should be added to the parameter . 3 . ac characteristics assume tt = 1 ns . if tr & tf > 1 ns, then [(tr+tf)/ 2 - 1 ]ns should be added to the parameter . 4 . thz defines the time at which the output achieves the open circuit condition ; it is not a reference to voh or vol . the last valid data element will meet toh before going high - z . 5 . parameter guaranteed by design . 6 . required clocks are specified by jedec functionality and are not dependent on any timing parameter . 7 . timing actually specified by tdpl plus trp ; clock(s) specified as a reference only at minimum cycle rate 8 . jedec and pc 100 specify three clocks . 9 . timing actually specified by tcks ; clock(s) specified as a reference only at minimum cycle rate . 10. a new command can be given trc after self refresh exit .
30 rev. a | mar. 2011 is42sm/rm/vm16200c www.issi.com - dram@issi.com temperature compensated self refresh temperature compensated self refresh allows the controller to program the refresh interval during self refresh mode, according to the case temperature of the low power sdram device . this allows great power savings during self refresh during most operating temperature ranges . only during extreme temperatures would the controller have to select a tcsr level that will guarantee data during self refresh . every cell in the dram requires refreshing due to the capacitor losing its charge over time . the refresh rate is dependent on temperature . at higher temperatures a capacitor loses charge quicker than at lower temperatures, requiring the cells to be refreshed more often . historically, during self refresh, the refresh rate has been set to accommodate the worst case, or highest temperature range expected . thus, during ambient temperatures, the power consumed during refresh was unnecessarily high, because the refresh rate was set to accommodate the higher temperatures . setting m 4 and m 3 , allow the dram to accommodate more specific temperature regions during self refresh . there are four temperature settings, which will vary the self refresh current according to the selected temperature . this selectable refresh rate will save power when the dram is operating at normal temperatures . partial array self refresh for further power savings during self refresh, the pasr feature allows the controller to select the amount of memory that will be refreshed during self refresh . the refresh options are two bank ; all two banks, one bank ; bank a . write and read commands can still occur during standard operation, but only the selected banks will be refreshed during self refresh . data in banks that are disabled will be lost . deep power down deep power down is an operating mode to achieve maximum power reduction by eliminating the power of the whole memory array of the devices . data will not be retained once the device enters deep power down mode . this mode is entered by having all banks idle then /cs and /we held low with /ras and /cas held high at the rising edge of the clock, while cke is low . this mode is exited by asserting cke high . special operation for low power consumption
31 rev. a | mar. 2011 is42sm/rm/vm16200c www.issi.com - dram@issi.com figure7: deep power down mode entry figure8: deep power down mode exit /cs /ras /cas /we clk cke 100 s trp trfc deep power down exit all banks precharge auto refresh mode register set extended mode register set new command auto refresh don?t care clk cke precharge if needed deep power down entry trp /cs /ras /cas /we don?t care
32 rev. a | mar. 2011 is42sm/rm/vm16200c www.issi.com - dram@issi.com
33 rev. a | mar. 2011 is42sm/rm/vm16200c www.issi.com - dram@issi.com ordering information ? vdd = 1.8v configuration frequency (mhz) speed (ns) order part no. package 2mx16 166 6 is42vm16200c - 6bli 54- ball bga, lead - free 133 7.5 is42vm16200c - 75bli 54- ball bga, lead - free industrial range: ( - 40 o c to +85 o c) ordering information ? vdd = 2.5v configuration frequency (mhz) speed (ns) order part no. package 2mx16 166 6 is42rm16200c - 6bli 54- ball bga, lead - free 133 7.5 is42rm16200c - 75bli 54- ball bga, lead - free industrial range: ( - 40 o c to +85 o c) ordering information ? vdd = 3.3v configuration frequency (mhz) speed (ns) order part no. package 2mx16 166 6 IS42SM16200C - 6bli 54- ball bga, lead - free 133 7.5 IS42SM16200C - 75bli 54- ball bga, lead - free industrial range: ( - 40 o c to +85 o c)

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